In IC design, more and more functionality is being designed for incorporating more power processors into smaller integrated circuits, also known as systems on chip (SoC). These processors require complex design and manufacturing efforts, which are only escalating given present user and device demands for additional performance, function, and particularly mobility. Unfortunately, with increasing demands comes increased pressures on production cycle time and a premium demand for improved utilization of both the available footprint as well as the power management aspects of the processor or SoC.
In particular, there is an increasing demand for low-power designs given the increased demand for battery-based mobility needs. Similarly, designs are also being pressured to account and lower power losses due to current leakage issues. As a result, one approach to improve battery and power performance includes turning off the associated logic, requiring power management inside the SoC. Other earlier approaches have also included gating clocks in relation to inactive functions for more traditional circuits and then providing a “wake up” to the idled function. However, for SoCs, such traditional approaches are unsatisfactory, in part, as SoC power management is complex and needs to account for multiple power domains.
Power domains or power islands are power (or voltage-specific) areas of a specific voltage within a SoC. The power islands in a SoC provide for the independent voltage level and frequency operation within specific areas of the SoC footprint, usually providing power to those associated functions having that specific power need.
FIG. 1 depicts an example of an SoC 100. From FIG. 1, the SOC 100 has a portion 105 and power domains are designed within the circuitry of the SOC 100. Input/Output (I/O) cells are depicted at 120 though their particular orientation and arrangement may vary. Physical layer (PHY) logic 130 of the processor is in communication with a dynamic random access memory (DRAM) 150 via I/O buffer 180.
Examples of power domains include a core logic power domain, a protocol bridge power domain, an internal memory power domain, and an input/output (I/O) level. Examples of other domains may include a peripheral interface power domain, cache power domain, etc. In some SoCs there may further exist an “always on” power domain.
Each power domain typically has a representative voltage source associated with it, where, for example, the core logic power domain is 0.9 v and the I/O level power domain is 1.2 v. Further, power islands provide for the ability to isolate portions of the chip in terms of both voltage and frequency. In operation, a SoC can rely on the presence and operation of each of the designed power domains for normal operation of all of its associated functions.
A processor may deploy Power Shut-Off (PSO) techniques, such as power gating, to switch off power to parts of a chip when those certain blocks of that chip are not in use. For PSO, there may be power switches that are within the SoC control (i.e., chip shut-off) or there may be power switches which are external to the chip (i.e., off-chip shut-off). For on-chip shut-off, PSO approaches also typically require isolators (i.e., isolation cells) close or proximate to the PSO domain, but often the isolators are resident in an always-on domain or similar, as isolators require power. Similarly, for off-chip shut-off, PSO approaches also require isolators and additional circuit complexities which may also prove less reliable. Where a chip has multiple power domains, additional issues can arise concurrent with those above adding further concern.
FIG. 2 depicts a representative I/O cell 200 of an SoC having a plurality of isolation cells proximate to and external from the respective power domains. In FIG. 2, the I/O cell 200 has a core logic power domain at 212 and 232. In an embodiment, the core logic power domain is 0.9 v. Power from core logic power domain 212 is provided to the PHY logic 210 where at 214 the power may be disconnected when the device is in shut off or a reduced power mode or similar. Power provided to the PHY logic 210 may then be provided to the isolation control 220, in relation to that power provided directly to the isolation control 220 from a separate core power domain source 232. Core power domain source 232 provides power to the isolation control 220, the I/O logic 230 and the level shifter 240.
In operation, power to the isolation control 220 in the arrangement of FIG. 2 must also be maintained so as to ensure the logic is active (i.e., on) such that the signal on the I/O buffer 250 can be identified.
An I/O Level power domain 252 is provided to the functions associated with the I/O buffer 250 and the level shifter 240. The level shifter 240 provides functionality to translate voltages levels between the various power domains.
Unfortunately, these approaches each involve isolators external to the subject power domain, require multiple power domains to be operational for PSO, and may cause the I/O cell 200 to fall into an unknown state. This requires the use of three power domains so as to ensure the isolation logic is actively on so the signal on the I/O buffer can be identified.
What is desired is a method and circuit that addresses the above identified issues. The method and circuit should be simple, and easily implemented on existing designs. The present invention addresses such a need.